ARM 9
Instruction Set Architecture
C an users view introduction with performance perspective
Abstract:
ARM-processor family positions
among the leaders in key embedded applications, such as cell phone, PDA, and
HDD. Many presentations and short lectures have addressed the ARMs
applications and capabilities. In this introduction, we also highlight the
ARMs instruction set uniqueness from the performance prospective.
Processor instruction set
architecture (ISA) choices have seen evolved from accumulator, stack,
register-to-memory, to register-register (load-store) organization. ARM 9
ISA is a load-store machine. ARM 9 ISA takes the advantage of its smaller
set of visible registers (than some embedded processors) to incorporate more
direct controls and achieving high coding encoding density. For example,
ARMs load and store multiple register instruction allows enlisting of all
possible register choices and conditional execution in one instruction.
The Thumb mode instruction set is
another example of how ARM ISA facilitates higher encode density. Rather
than compressing the code, thumb-mode instructions are two 16-bit
instructions packed in a 32-bit ARM-mode instruction space. The Thumb-mode
instructions are subset of ARM instructions. When executing in Thumb mode, a
single 32-bit instruction fetch cycle effectively brings in two
instructions. Effectively, Thumb mode improves access bandwidth, code size,
and instruction cache hit rate.
In summary, ARM ISA effects high
functional density for control and many other key embedded applications. The
separate instruction and data buses relax peak memory bandwidth and hence
potential lower CPI (cycles per instruction). This introduction is intended
for audience with basic engineering but no specific ARM background.
References
|
Furber00 |
Steve Furber, ARM
System-on-chip Architecture, ISBN 0-201-67519-6, Addison-Wesley |
|
Seal00 |
David Seal, ARM
Architecture Reference Manual, ISBN 0-201- 737192, Addison-Wesley |
|
HenPet02 |
John L. Hennessy and David
A. Patterson, Computer Architecture - A Quantitative Approach,
Morgan Kaufmann, SF, CA |
|
PetHen00 |
David A. Patterson and John
L. Hennessy ,Computer Organization and Design, Morgan Kaufmann,
SF, CA |
|
IBM96 |
Hoxey et al edited, The
PowerPC Compiler Writers Guide, ISBN 0-9649654-0-2, Warthman
Associates |
Biography:
Joe-Ming Cheng has worked for IBM Research and Development for over 25 years
on algorithm, SOC, storage system, embedded system, and design automation
tool developments. He has also been a part-time faculty at San Jose State
University and Silicon Valley University. He received an Outstanding
Innovation Award and an Outstanding Achievement Award from IBM, and Patent
Awards on eight issued U.S. Patents. He has also worked on guidance system
and air-borne CPU developments. Dr. Cheng received an M.S. in Scientific
(Biomedical Electronics) Instrumentation, UC Santa Barbara, and a Ph.D. in
Computer Engineering, UC Santa Cruz.
